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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 tps54116-q1 2.95-v to 6-v input, 4-a step-down converter and 1-a source/sink ddr termination regulator 1 1 features 1 ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to +125 c ambient operating temperature range ? device hbm esd classification level 2 ? device cdm esd classification level c6 ? single-chip ddr2, ddr3 and ddr3l memory power solution ? 4-a synchronous buck converter ? integrated 33-m high-side and 25-m low- side mosfets ? fixed frequency current-mode control ? adjustable frequency from 100 khz to 2.5 mhz ? synchronizable to an external clock ? 0.6-v 1% voltage reference over temperature ? adjustable cycle-by-cycle peak current limit ? monotonic start-up into pre-biased outputs ? 1-a source/sink termination ldo with 20-mv dc accuracy ? stable with 2 10- f mlcc capacitor ? 10-ma source/sink buffered reference output regulated to within 49% to 51% of vddq ? independent enable pins with adjustable uvlo and hysteresis ? thermal shutdown ? -40 c to 150 c operating t j ? 24-pin, 4-mm x 4-mm wqfn package 2 applications ? ddr2, ddr3, ddr3l, and ddr4 memory power supplies in embedded computing systems ? sstl_18, sstl_15, sstl_135, sstl_12 and hstl termination ? infotainment and cluster ? advanced driver assistance systems (adas) 3 description the tps54116-q1 device is a full featured 6-v, 4-a, synchronous step down converter with two integrated mosfets and 1-a sink/source double date rate (ddr) vtt termination regulator with vttref buffered reference output. the tps54116-q1 buck regulator minimizes solution size by integrating the mosfets and reducing inductor size with up to 2.5-mhz switching frequency. the switching frequency can be set above the medium wave radio band for noise sensitive applications and is synchronizable to an external clock. synchronous rectification keeps the frequency fixed across the entire output load range. efficiency is maximized through integrated 25-m low-side and 33-m high-side mosfets. cycle-by-cycle peak current limit protects the device during an overcurrent condition and is adjustable with a resistor at the ilim pin to optimize for smaller inductors. the vtt termination regulator maintains fast transient response with only 2 10- f ceramic output capacitance reducing external component count. the tps54116-q1 uses remote sensing of vtt for best regulation. using the enable pins to enter a shutdown mode reduces supply current to 1- a. under voltage lockout thresholds can be set with a resistor network on either enable pin. the vtt and vttref outputs are discharged when disabled with enldo. full integration minimizes the ic footprint with a small 4 mm 4 mm thermally enhanced wqfn package. device information (1) part number package body size (nom) tps54116-q1 wqfn (24) 4.00 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. simplified schematic ensw pgood sw boot pvin pgnd enldo ilim vddqsns comp vtt vttgnd vttsns avin ldoin ss/trk fb v ddq v in v tt vttref agnd rt/sync v ttref v in pad tps54116-q1 copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 8 7 detailed description ............................................ 15 7.1 overview ................................................................. 15 7.2 functional block diagram ....................................... 16 7.3 feature description ................................................. 17 7.4 device functional modes ........................................ 23 8 application and implementation ........................ 24 8.1 application information ............................................ 24 8.2 typical application ................................................. 25 9 power supply recommendations ...................... 34 10 layout ................................................................... 34 10.1 layout guidelines ................................................. 34 10.2 layout example .................................................... 35 11 device and documentation support ................. 36 11.1 receiving notification of documentation updates 36 11.2 community resources .......................................... 36 11.3 trademarks ........................................................... 36 11.4 electrostatic discharge caution ............................ 36 11.5 glossary ................................................................ 36 12 mechanical, packaging, and orderable information ........................................................... 36 4 revision history changes from original (august 2016) to revision a page ? changed pin 18 from: rt/clk to: rt/sync in the pin functions table ............................................................................. 4 ? changed r (rt/clk) to: r (rt/sync) in figure 16 and figure 17 .................................................................................................. 9 ? changed " the rt/clk is typically 0.5 v.. " to: " the rt/sync is typically 0.5 v.. " in constant switching frequency and timing resistor (rt/sync) .......................................................................................................................................... 20
3 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions rtw package wqfn 24 pins top view pin functions pin i/o description name no. sw 1, 23, 24 o switching node of the buck converter. boot 2 i bootstrap capacitor node for high-side mosfet gate driver of the buck converter. connect the bootstrap capacitor from this pin to the sw pin. avin 3 i the input supply pin to the ic, powering the control circuits of both the buck converter and ddr termination regulator. connect avin to a supply voltage between 2.95 v and 6 v. ensw 4 i buck converter enable pin with internal pull-up current source. floating this pin will enable the ic. pull below 1.17 v to enter low current standby mode. pull below 0.4 v to enter shutdown mode. the ensw pin can be used to implement adjustable under-voltage lockout (uvlo) using two resistors. enldo 5 i vtt ldo enable pin with internal pull-up current source. floating this pin will enable the ic. pull below 1.17 v to enter low current standby mode. pull below 0.4 v to enter shutdown mode. the enldo pin can be used to implement adjustable under-voltage lockout (uvlo) using two resistors. pgood 6 o power good indicator for the buck regulator. this pin is an open-drain output. a 10-k pull- up resistor is recommended between pgood and avin or an external logic supply pin. vddqsns 7 i vddq sense input to generate vddq/2 reference for vttref. ldoin 8 i power supply input for vtt ldo. connected vddq in typical application. alternatively this pin can be used for split-rail configuration to reduce power dissipation when sourcing current to the vtt output by powering the vtt ldo with a lower voltage. vtt 9 o 1-a ldo output. connect 2 x 10- f ceramic capacitors to vttgnd for stability. vttgnd 10 i power ground for vtt ldo. vttsns 11 i vtt ldo voltage feedback. vttref 12 o buffered low-noise vtt reference output. connect to a 0.22 f or larger ceramic capacitor to agnd for stability. ilim 13 i programmable current limit pin. an internal amplifier holds this pin at a fixed voltage then sets the high-side mosfet peak current limit based on the value of an external resistor to agnd. agnd 14 i analog signal ground of the ic. agnd should be connected to pgnd via a single point on the pcb, typically to the thermal pad. sw boot ensw pgood avin enldo sw pvin pgnd pvin pgnd sw rt/sync agnd ss/trk ilim fb comp vttref vldoin vtt vttsns vddqsns vttgnd 6 5 4 3 2 1 7 8 9 10 11 12 24 23 22 21 20 19 13 14 15 16 17 18 pad
4 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated pin functions (continued) pin i/o description name no. fb 15 i error amplifier inverting input and feedback pin for voltage regulation of the buck converter. connect this pin to the center of a resistor divider to set the output voltage of the buck converter. the resistor divider should go from the regulated output voltage to agnd. comp 16 i output of the internal transconductance error amplifier for the buck converter. the feedback loop compensation network is connected from this pin to agnd. ss/trk 17 i soft-start programming pin. a capacitor between the ss/trk pin and agnd pin sets soft- start time. the voltage on this pin overrides the internal reference allowing it to be used for tracking and sequencing. rt/sync 18 i resistor timing and external clock. an internal amplifier holds this pin at a fixed voltage when using an external resistor to agnd to set the switching frequency. if the pin is pulled above the upper threshold, a mode change occurs and the pin becomes a synchronization input. the internal amplifier is disabled and the pin is a high impedance clock input. if clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. pgnd 19, 20 i power ground of the buck regulator. pgnd should be connected to agnd via a single point on pcb board, typically to the thermal pad. pvin 21, 22 i the input supply pin for power mosfets. connect pvin to a supply voltage between 2.95 v and 6 v. pad ? the exposed thermal pad must be electrically connected to agnd and pgnd on the printed circuit board for proper operation. connect to the largest possible copper area for best thermal performance. (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit voltage range pvin, avin, ensw, enldo, pgood -0.3 7 v fb, comp, ss/trk, ilim -0.3 3 v rt/sync -0.3 6 v boot with respect to sw -0.3 7 v ldoin, vttsns, vddqsns -0.3 3.6 v sw -0.6 7 v sw, 10-ns transient -4 10 v vtt, vttref -0.3 3.6 v current range rt/sync -100 100 a pgood -5 5 ma operating junction temperature -40 150 c storage temperature, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 1000
5 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit v (avin) , v (pvin) input voltage 2.95 6 v v out buck output voltage 0.6 4.5 v i out buck output current 0 4 a v (vddqsns) vddqsns input voltage 1 3.5 v v (ldoin) ldoin input voltage vtt + vdo 3.5 v v (vtt) , v (vttref) vtt and vttref output voltage 0.5 3.5 v (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report. 6.4 thermal information thermal metric (1) tps54116-q1 unit rtw (wqfn) 24 pins r ja junction-to-ambient thermal resistance 36.2 c/w r jc(top) junction-to-case (top) thermal resistance 35.0 r jb junction-to-board thermal resistance 14.3 jt junction-to-top characterization parameter 0.4 jb junction-to-board characterization parameter 14.4 r jc(bot) junction-to-case (bottom) thermal resistance 4.6 6.5 electrical characteristics tj = -40 c to 150 c, avin = pvin = 2.95 v to 6 v, vldoin = vddqsns (unless otherwise noted) parameter test conditions min typ max unit supply voltage (avin and pvin pins) avin and pvin operating 2.95 6 v avin internal uvlo threshold avin rising 2.7 2.8 v avin internal uvlo hysteresis 0.05 0.12 v iq shutdown v (ensw) = v (enldo) = 0 v, v (vddqsns) = 1.8 v, tj = 25 c 1 3.5 a iq operating ? ldo and buck enabled v (ensw) = v (enldo) = v (avin) = 5 v, v (fb) = 0.7 v, v (vddqsns) = 1.8 v, tj = 25 c 650 800 a iq operating ? ldo enabled, buck disabled v (enldo) = v (avin) = 5 v, v (ensw) = 0 v, v (vddqsns) = 1.8 v, tj = 25 c 190 300 a iq operating ? ldo disabled, buck enabled v (ensw) = v (avin) = 5 v, v (enldo) = 0 v, v (fb) = 0.7 v, v (vddqsns) = 1.8 v, tj = 25 c 570 700 a enable (ensw and enldo pins) v enrising enldo rising threshold enldo voltage ramping up 1.20 v v enfalling enldo falling threshold enldo voltage ramping down 1.17 enldo input current above voltage threshold v (enldo) = enable threshold + 50 mv -4.4 a i p enldo input current below voltage threshold v (enldo) = enable threshold - 50 mv -1.7 i h enldo hysteresis current -2.7 v enrising ensw rising threshold ensw voltage ramping up 1.20 v v enfalling ensw falling threshold ensw voltage ramping down 1.17 ensw input current above voltage threshold v (ensw) = enable threshold + 50 mv -4.4 a i p ensw input current below voltage threshold v (ensw) = enable threshold - 50 mv -1.7 i h ensw hysteresis current -2.7 input current above voltage threshold with enldo and ensw connected v (enldo) = v (ensw) = enable threshold + 50 mv -8.5 a
6 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) tj = -40 c to 150 c, avin = pvin = 2.95 v to 6 v, vldoin = vddqsns (unless otherwise noted) parameter test conditions min typ max unit input current below voltage threshold with enldo and ensw connected v (enldo) = v (ensw) = enable threshold - 50 mv -3.4 a hysteresis current with enldo and ensw connected -5.1 a voltage reference and error amplifier (fb and comp pins) v ref voltage reference 0.594 0.6 0.606 v fb pin input current 7 na gm ea error amp transconductance (gm) -2 a < i (comp) < 2 a, v (comp) = 1 v 260 360 s error amp source/sink v (comp) = 1 v, v (fb) = 100 mv overdrive 22 a mosfets and power stage (sw and boot pins) high side switch resistance v (boot-sw) = 5 v 33 66 m v (boot-sw) = 3.3 v 42 84 low side switch resistance v (pvin) = 5 v 25 50 m v (pvin) = 3.3 v 30 60 boot-sw uvlo v (pvin) = 2.95 v 2.2 v high-side fet current limit v (pvin) = 6v, r (ilim) = 100k 5.2 6.6 8.2 a high-side fet current limit v (pvin) = 6v, r (ilim) = 200k 1.5 3 3.8 a low-side fet reverse current limit 2 4.5 a gm ps v (comp) to i (sw) peak transconductance r (ilim) = 100k 16 a/v minimum pulse width measured at 50% points on v (sw) , i out = 2 a 60 ns minimum pulse width measured at 50% points v (sw) , v (pvin) = 5 v, i out = 0 a, tj = -40 c to 125 c 100 125 ns minimum off-time prior to skipping off pulses, i out = 2 a 60 ns timing resistor and external clock (rt/sync pin) switching frequency range using rt mode 100 2500 khz switching frequency r (rt/sync) = 150 k 370 400 430 khz r (rt/sync) = 27 k 1910 2070 2230 khz v (rt/sync) > 2.2 v or v (rt/sync) < 0.35 v 340 420 480 khz switching frequency range using sync mode 100 2500 khz minimum sync input pulse width 10 ns rt/sync high threshold 1.5 2.2 v rt/sync low threshold 0.35 0.4 v rt/sync rising edge to sw rising edge delay f sw = 500 khz 30 45 80 ns rt to sync lock in time r (rt/sync) = 150 k 55 s sync to rt lock in time 60 s internal rt to sync lock in time logic high or logic low at rt/sync to sync signal 55 s sync to internal rt lock in time sync signal to logic high or logic low at rt/sync 60 s soft start and tracking (ss/trk pin) v ssthr ss voltage threshold 0.15 v i ss charge current v (ss/trk) < v ssthr 47 a v (ss/trk) > v ssthr 1.5 2.4 3.2 a ss/trk to fb matching v (ss/trk) = 0.3 v 60 mv ss/trk to reference crossover 98% normal 0.85 1 v ss/trk discharge voltage (overload) v (fb) = 0 v 120 mv ss/trk discharge voltage (fault) v (fb) = 0 v 5 mv ss/trk discharge current (overload) v (fb) = 0 v, v (ss/trk) = 0.4 v 160 a
7 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) tj = -40 c to 150 c, avin = pvin = 2.95 v to 6 v, vldoin = vddqsns (unless otherwise noted) parameter test conditions min typ max unit ss/trk discharge current (avin uvlo, ensw low, thermal fault) v (avin) = 5 v, v (ss/trk) = 0.4 v 760 a power good (pgood pin) threshold v (fb) falling (fault) 91 95 % v ref v (fb) rising (good) 94 v (fb) rising (fault) 105 109 v (fb) falling (good) 106 hysteresis v (fb) falling and rising 3 output high leakage v (fb) = v ref , v (pgood) = 5.5 v 5 125 na on resistance v (avin) = 2.95 v 85 170 minimum v (avin) for valid output v (pgood) < 0.5 v, i (pgood) = 100 a 1.3 1.7 v termination regulator inputs (vldoin and vddqsns pins) v (ldoin) operating 3.5 v v do dc v (ldoin) ? v (vtt) dropout 1.2 v < v (vddqsns) < 2.5 v, i (vtt) = 0.5 a, v (vtt) = v (vttref) - 40 mv 0.15 v v do dc v (ldoin) ? v (vtt) dropout 1.2 v < v (vddqsns) < 2.5 v, i (vtt) = 1.5 a, v (vtt) = v (vttref) - 40 mv 0.45 v vldoin supply current v (ldoin) = 1.8 v, tj = 25 c 1 a vddqsns input current v (vddqsns) = 1.8 v 39 46 a vttref output (vttref pin) v (vttref) vttref output voltage v (vddqsns) /2 v v (vttref)tol vttref output voltage difference from v (vddqsns) /2 |i (vttref) | < 10 ma, v (vddqsns) = 1.8 v -18 18 mv |i (vttref) | < 10 ma, v (vddqsns) = 1.5 v -15 15 |i (vttref) | < 10 ma, v (vddqsns) = 1.2 v -15 15 |i (vttref) | < 5 ma, v (vddqsns) = 1.2 v -12 12 i (vttref)src vttref source current limit v (vddqsns) = 1.8 v, v (vttref) = 0 v 10 18 ma i (vttref)snk vttref sink current limit v (vddqsns) = 0 v, v (vttref) = 1.8 v 10 19 ma i (vttref)dis vttref discharge current tj = 25 c, v (vttref) = 0.5v, v (enldo) = 0 v 0.9 1.1 ma vtt output (vtt pin) v (vtt) vtt output voltage v (vttref) v v (vtt)tol vtt output voltage tolerance to vttref |i (vtt) | 10 ma, 1.2 v v (vddqsns) 1.8 v -20 20 mv |i (vtt) | 1 a, 1.2 v v (vddqsns) 1.8 v -30 30 |i (vtt) | 1.5 a, 1.2 v v (vddqsns) 1.8 v -40 40 i (vtt)src vtt source current limit v (vddqsns) = 1.8 v, v (vtt) = v (vttsns) = 0.7 v 1.5 2.5 a i (vtt)snk vtt sink current limit v (vddqsns) = 1.8 v, v (vtt) = v (vttsns) = 1.1 v 1.5 2.5 a i (vttsns)bias vttsns input bias current -0.1 0.1 a i (vtt)dis vtt discharge current tj = 25 c, v (vtt) = 0.5 v, v (enldo) = 0 v 4.8 6 ma thermal shutdown thermal shutdown temperature 175 thermal shutdown hysteresis 16
8 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.6 typical characteristics figure 1. shutdown supply current vs temperature figure 2. non-switching supply current - ldo and buck enabled vs temperature figure 3. non-switching supply current - ldo enabled and buck disabled vs temperature figure 4. non-switching supply current - ldo disabled and buck enabled vs temperature figure 5. ensw and enldo voltage threshold vs temperature figure 6. ensw and enldo individual input current vs temperature junction temperature ( q c) nonswitching supply current ( p a) -50 -25 0 25 50 75 100 125 150 555 560 565 570 575 580 585 590 595 600 605 610 d004 v in = 3.3 v v in = 5 v junction temperature ( q c) shutdown supply current ( p a) -50 -25 0 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 d001 v in = 3.3 v v in = 5 v junction temperature ( q c) nonswitching supply current ( p a) -50 -25 0 25 50 75 100 125 150 600 625 650 675 700 725 750 775 800 d002 v in = 3.3 v v in = 5 v junction temperature ( q c) ensw and enldo individual input current ( p a) -50 -25 0 25 50 75 100 125 150 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 d006 v (en) = threshold - 50 mv v (en) = threshold + 50 mv junction temperature ( q c) ensw and enldo voltage threshold (v) -50 -25 0 25 50 75 100 125 150 1.16 1.165 1.17 1.175 1.18 1.185 1.19 1.195 1.2 1.205 1.21 d005 en rising en falling junction temperature ( q c) nonswitching supply current ( p a) -50 -25 0 25 50 75 100 125 150 125 150 175 200 225 250 275 300 325 d003 v in = 3.3 v v in = 5 v
9 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 7. ensw and enldo parallel input current vs temperature figure 8. voltage reference vs temperature figure 9. error amplifier transconductance vs temperature figure 10. mosfet r ds(on) vs temperature v (pvin) = 5 v figure 11. high-side current limit vs temperature v (pvin) = 5 v t a = 25 c figure 12. high-side current limit vs r ilim junction temperature ( q c) high-side current limit (a) -50 -25 0 25 50 75 100 125 150 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 d011 r (ilim) = 100 k r (ilim) = 200 k r(ilim) high-side current limit (a) 100 110 120 130 140 150 160 170 180 190 200 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 d012 junction temperature ( q c) error amplifier transconductance ( p s) -50 -25 0 25 50 75 100 125 150 200 220 240 260 280 300 320 d009 junction temperature ( q c) mosfet r ds(on) (m : ) -50 -25 0 25 50 75 100 125 150 15 20 25 30 35 40 45 50 55 60 65 70 75 d010 high-side, v (boot-sw) = 3.3 v high-side, v (boot-sw) = 5 v low-side, v (pvin) = 3.3 v low-side, v (pvin) = 5 v junction temperature ( q c) ensw and enldo parallel input current ( p a) -50 -25 0 25 50 75 100 125 150 -10 -9 -8 -7 -6 -5 -4 -3 -2 d007 v (en) = threshold - 50 mv v (en) = threshold + 50 mv junction temperature ( q c) voltage reference (v) -50 -25 0 25 50 75 100 125 150 0.594 0.595 0.596 0.597 0.598 0.599 0.6 0.601 0.602 0.603 0.604 0.605 0.606 d008
10 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 13. v (comp) to i (sw) transconductance vs temperature figure 14. minimum pulse-width vs temperature t a = 25 c figure 15. minimum pulse-width vs load current t a = 25 c figure 16. switching frequency vs r (rt/sync) low range t a = 25 c figure 17. switching frequency vs r (rt/sync) high range r (rt/sync) = 150 k figure 18. switching frequency vs temperature iout (a) minimum pulse-width (ns) 0 0.5 1 1.5 2 2.5 3 3.5 4 55 60 65 70 75 80 85 90 95 100 d015 v in = 3.3 v v in = 5 v r (rt/sync) (k : ) switching frequency 100 150 200 250 300 350 400 450 500 550 600 650 100 150 200 250 300 350 400 450 500 550 600 650 d016 ambient temperature ( q c) v (comp) to i (sw) transconductance (s) -50 -25 0 25 50 75 100 125 150 12 13 14 15 16 17 18 19 d013 v in = 3.3 v v in = 5 v ambient temperature ( q c) minimum pulse-width (ns) -50 -25 0 25 50 75 100 125 40 50 60 70 80 90 100 110 120 130 140 d014 v in = 3.3 v, i out = 0 a v in = 5 v, i out = 0 a v in = 3.3 v, i out = 2 a v in = 5 v, i out = 2 a r (rt/sync) (k : ) switching frequency 20 30 40 50 60 70 80 90 100 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 d017 junction temperature ( q c) switching frequency (khz) -50 -25 0 25 50 75 100 125 150 390 392 394 396 398 400 402 404 406 408 410 d018
11 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) r (rt/sync) = 27 k figure 19. switching frequency vs temperature internal rt figure 20. switching frequency vs temperature v (ss/trk) < v ss(thr) figure 21. i (ss/trk) vs temperature v (ss/trk) > v ss(thr) figure 22. i (ss/trk) vs temperature t a = 25 c figure 23. v (fb) vs v (ss/trk) figure 24. pgood thresholds vs temperature v (ss/trk) (v) v (fb) (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 d023 junction temperature ( q c) pgood threshold ( of v ref ) -50 -25 0 25 50 75 100 125 150 90 92 94 96 98 100 102 104 106 108 110 d024 v (fb) falling (fault) v (fb) rising (good) v (fb) rising (fault) v (fb) falling (good) junction temperature ( q c) i (ss/trk) (a) -50 -25 0 25 50 75 100 125 150 51 51.5 52 52.5 53 53.5 54 54.5 55 d021 junction temperature ( q c) i (ss/trk) (a) -50 -25 0 25 50 75 100 125 150 2.34 2.36 2.38 2.4 2.42 2.44 2.46 2.48 2.5 d022 junction temperature ( q c) switching frequency (khz) -50 -25 0 25 50 75 100 125 150 2060 2062 2064 2066 2068 2070 2072 2074 2076 2078 2080 d019 junction temperature ( q c) switching frequency (khz) -50 -25 0 25 50 75 100 125 150 400 405 410 415 420 425 430 d020
12 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) vddqsns = 1.8 v v in = 5 v figure 25. vttref regulation to vddqsns/2 vs i (vttref) vddqsns = 1.5 v v in = 5 v figure 26. vttref regulation to vddqsns/2 vs i (vttref) vddqsns = 1.35 v v in = 5 v figure 27. vttref regulation to vddqsns/2 vs i (vttref) vddqsns = 1.2 v v in = 5 v figure 28. vttref regulation to vddqsns/2 vs i (vttref) vddqsns = 1.8 v v in = 5 v figure 29. vtt regulation to vttref vs i (vtt) vddqsns = 1.5 v v in = 5 v figure 30. vtt regulation to vttref vs i (vtt) vtt current (a) vtt regulation (mv) -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25 d030 t a = -40 c t a = 25 c t a = 125 c vttref current (ma) vttref regulation (mv) -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 d026 t a = -40 c t a = 25 c t a = 125 c vttref current (ma) vttref regulation (mv) -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 d026 t a = -40 c t a = 25 c t a = 125 c vttref current (ma) vttref regulation (mv) -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 d026 t a = -40 c t a = 25 c t a = 125 c vttref current (ma) vttref regulation (mv) -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 d026 t a = -40 c t a = 25 c t a = 125 c vtt current (a) vtt regulation (mv) -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25 d030 t a = -40 c t a = 25 c t a = 125 c
13 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) vddqsns = 1.35 v v in = 5 v figure 31. vtt regulation to vttref vs i (vtt) vddqsns = 1.2 v v in = 5 v figure 32. vtt regulation to vttref vs i (vtt) vddqsns = 1.5 v v in = 5 v figure 33. vtt dropout v (vtt) = 1.5 v v in = 5 v i (vtt) = +1 a t a = 25 c figure 34. vtt sourcing frequency response v (vtt) = 1.5 v v in = 5 v i (vtt) = ? 1 a t a = 25 c figure 35. vtt sinking frequency response f sync = 2.1 mhz v in = 3.3 v l = 744373240068 t a = 25 c figure 36. efficiency frequency (hz) gain (db) phase ( q ) 10000 100000 1000000 1e+7 -20 -100 -10 -50 0 0 10 50 20 100 30 150 40 200 d036 gain phase output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 50 55 60 65 70 75 80 85 90 95 100 d044 v ddq = 1.8 v v ddq = 1.5 v v ddq = 1.35 v v ddq = 1.2 v ivtt sourcing transient (a) minimum vldoin - vtt difference (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 d034 t a = -40 c t a = 25 c t a = 125 c frequency (hz) gain (db) phase ( q ) 10000 100000 1000000 1e+7 -20 -100 -10 -50 0 0 10 50 20 100 30 150 40 200 d035 gain phase vtt current (a) vtt regulation (mv) -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25 d030 t a = -40 c t a = 25 c t a = 125 c vtt current (a) vtt regulation (mv) -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 -25 -20 -15 -10 -5 0 5 10 15 20 25 d030 t a = -40 c t a = 25 c t a = 125 c
14 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) f sync = 2.1 mhz v in = 5 v l = 744373240068 t a = 25 c figure 37. efficiency f sync = 400 khz v in = 3.3 v l = 744310200 t a = 25 c figure 38. efficiency f sync = 400 khz v in = 5 v l = 744310200 t a = 25 c figure 39. efficiency output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 50 55 60 65 70 75 80 85 90 95 100 d047 v ddq = 1.8 v v ddq = 1.5 v v ddq = 1.35 v v ddq = 1.2 v output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 50 55 60 65 70 75 80 85 90 95 100 d045 v ddq = 1.8 v v ddq = 1.5 v output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 50 55 60 65 70 75 80 85 90 95 100 d046 v ddq = 1.8 v v ddq = 1.5 v v ddq = 1.35 v v ddq = 1.2 v
15 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the tps54116-q1 is a 6-v, 4-a, synchronous step-down (buck) converter with two integrated n-channel mosfets and integrated 1-a sink/source double data rate (ddr) vtt termination regulator with a vttref buffed reference output. to improve the performance during line and load transients the buck converter implements a constant frequency, peak current mode control which reduces output capacitance and simplifies external frequency compensation design. the wide switching frequency range of 100 khz to 2500 khz allows for efficiency and size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground on the rt/sync pin. the rt/sync pin can also be used to synchronize the power switch turn on to the rising edge of an external clock. the switching frequency can be set using an internal resistor by pulling the rt/sync below the low threshold or above the high threshold. the tps54116-q1 has a typical default start-up voltage of 2.7 v. the ensw pin can be used to enable the buck converter and the enldo pin can be used to enable vtt and vttref. the ensw and enldo pins have internal pullup current sources that can be used to adjust the input voltage under voltage lockout (uvlo) with two external resistors. in addition, the pullup current provides a default condition when the ensw or enldo pin is floating for the device to operate. the total operating current for the tps54116-q1 is typically 650 a when not switching and under no load. when the device is disabled, the supply current is less than 3.5 a. the integrated 33-m and 25-m mosfets allow for high-efficiency power supply designs with continuous output currents up to 4 amperes. the tps54116-q1 reduces the external component count by integrating the boot recharge diode. the bias voltage for the integrated high-side mosfet is supplied by a capacitor between the boot and sw pins. the boot capacitor voltage is monitored by an uvlo circuit and turns off the high-side mosfet when the voltage falls below the boot-sw uvlo threshold. this boot circuit allows the tps54116- q1 to operate approaching 100% duty cycle. the output voltage can be stepped down to as low as the 0.60-v reference. the tps54116-q1 features monotonic start-up under prebias conditions. the low-side fet turns on for a short time period every cycle before the output voltage reaches the prebiased voltage. this ensures the boot capacitor has enough charge to turn on the top fet when the output voltage reaches the prebiased voltage. the tps54116-q1 has a power good comparator (pgood) with 3% hysteresis. excessive output overvoltage transients are minimized by taking advantage of the overvoltage power good comparator. when the regulated output voltage (as sensed by the fb voltage) is greater than 109% of the nominal voltage, the overvoltage comparator is activated, and the high-side mosfet is turned off and masked from turning on until the output voltage is lower than 106%. the ss/trk (soft-start or tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. a small value capacitor should be coupled to the pin for soft-start. the ss/trk pin is discharged before the output power up to ensure a repeatable restart after an over temperature fault, uvlo fault or disabled condition. to optimize the output startup waveform, two levels of ss/trk output current are implemented. the tps54116-q1 limits the peak inductor current by sensing the current through the high-side mosfet with cycle-by-cycle protection. the peak current limit is adjusted using a resistor to ground on the ilim pin. the reverse current through the low-side mosfet is also limited. the 10-ma vttref buffered reference uses an internal resistor divider to regulate its output within 49% to 51% of vddqsns. the 1-a vtt termination regulates to vttref and maintains fast transient response with only 2 10- f ceramic output capacitance. remote sensing of vtt is used for best regulation. the vtt and vttref outputs are discharged when disabled with the avin uvlo or with enldo.
16 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.2 functional block diagram error amplifier current sense logic pwm latch pwm comparator fb ss/trk sw boot pvin 6 pgnd comp rt/sync uvlo comparator ovlo comparator vref_ov vref_uv pgood vddqsns vttref vldoin vtt vttgnd vttsns agnd ensw enable switcher ilim avin boot charge boot uvlo voltage reference ilim reference oscillator with sync enldo enable ldo slope compensation current limit s q q r shutdown shutdown pad maximum clamp current limit current sense copyright ? 2016, texas instruments incorporated
17 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.3 feature description 7.3.1 fixed frequency pwm control the tps54116-q1 uses an adjustable fixed frequency, peak current mode control. the output voltage is compared through external resistors on the fb pin to an internal voltage reference by an error amplifier which drives the comp pin. an internal oscillator initiates the turn on of the high-side power switch. the error amplifier output is compared to the high-side power switch current. when the power switch current reaches the comp signal level the high-side power switch is turned off and the low-side power switch is turned on. the comp pin voltage will increase and decrease as the output current increases and decreases. the device implements a current limit by clamping the internal comp signal. an internal ramp is used to provide slope compensation to prevent sub-harmonic oscillations. the peak inductor current limit is constant over the full duty cycle range. 7.3.2 bootstrap voltage (boot) and low dropout operation the tps54116-q1 has an integrated boot regulator and requires a small ceramic capacitor between the boot and sw pins to provide the gate drive voltage for the high-side mosfet. the value of the ceramic capacitor should be 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric is recommended because of the stable characteristics over temperature and voltage. to improve dropout, the tps54116-q1 is designed to operate at 100% duty cycle as long as the boot-sw voltage is greater than 2.2 v. the high-side mosfet is turned off using an uvlo circuit, allowing for the low- side mosfet to conduct, when the boot-sw voltage drops below 2.2 v. because the supply current sourced from the boot pin is low, the high-side mosfet can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty of the switching regulator is high. 7.3.3 error amplifier the tps54116-q1 has a transconductance amplifier for the error amplifier. the error amplifier compares the fb voltage to the lower of the ss/trk pin voltage or the internal 0.6-v voltage reference. the transconductance (gm ea ) of the error amplifier is 260 a/v during normal operation. during soft-start, the gm ea is reduced to 90 a/v. the frequency compensation components are added to the comp pin to ground. when operating at current limit the comp pin voltage is clamped to a maximum level to improve response when the load current decreases. when fb is greater than the internal voltage reference or ss/trk the comp pin voltage is clamped to a minimum level and the devices enters a high-side skip mode. 7.3.4 voltage reference and adjusting the output voltage the voltage reference system produces a precise 1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. the fb voltage is regulated to the voltage reference. the output voltage is set with a resistor divider from the output node to the fb pin. it is recommended to use divider resistors with 1% tolerance or better. start with a 10.0 k ? for the bottom resistor r fbb and use the equation 1 to calculate r fbt . the maximum recommend resistance value for the bottom resistor is 100 k . vertical spacer (1) out fbt fbb ref v r r 1 v u ? ? 1
18 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 40. voltage divider circuit 7.3.5 enable and adjusting undervoltage lockout the tps54116-q1 is enabled when the avin pin voltage exceeds 2.7 v and is disabled when it falls below 2.65 v. if an application requires a higher under-voltage lockout (uvlo) or more hysteresis, use the ensw or enldo pins as shown in figure 41 to adjust the input voltage uvlo by using two external resistors. the en pin has an internal pull-up current source (i p ) of 1.7 a that provides the default condition of the tps54116-q1 operating when the en pin floats. once the en pin voltage exceeds 1.2 v, an additional 2.7 a hysteresis current (i h ) is added. when the en pin is pulled below 1.17 v, the 2.7 a is removed. this additional current facilitates input voltage hysteresis. it is recommended to use the en resistors to set the uvlo falling threshold (v stop ) at 2.65v or higher. the rising threshold (v start ) should be set to provide enough hysteresis to allow for any input supply variations. equation 2 can be used to calculate the top resistor in the en divider and equation 3 is used to calculate the bottom resistor. the ensw and enldo can also be tied in parallel. calculations can be done the same but with the increased en current of i p = 3.4 a and i h = 5.1 a. figure 41. adjustable under voltage lock out tps54116-q1 avin enldo or ensw r ent r enb i h + i p tps54116-q1 v out fb r fbt r fbb + 0.6 v
19 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) (2) vertical spacer (3) where: ? i h = 2.7 a ? i p = 1.7 a ? v enrising = 1.2 v ? v enfalling = 1.17 v 7.3.6 soft start and tracking the tps54116-q1 regulates to the lower of the ss/trk pin and the internal reference voltage. a capacitor on the ss/trk pin to ground implements a soft start time. before the ss pin reaches the voltage threshold v ssthr of 0.15 v, the charge current is about 47 a. the tps54116-q1 internal pull-up current source of 2.4 a charges the external soft start capacitor after the ss pin voltage exceeds v ssthr . equation 4 calculates the required soft start capacitor value where t ss is the desired soft start time for the output voltage to reach 90% its final value in ms and c ss is the required capacitance in nf. vertical spacer (4) if during normal operation, avin goes below the uvlo, ensw pin pulled below 1.17 v, or a thermal shutdown event occurs, the tps54116-q1 stops switching. when the avin goes above uvlo, ensw is released or pulled high, or a thermal shutdown is exited, then ss/trk is discharged to below 5 mv before reinitiating a powering up sequence. the fb voltage will follow the ss/trk pin voltage with a 60 mv offset up to 90% of the internal voltage reference. when the ss/trk voltage is greater than 90% of the internal reference voltage the offset increases as the effective system reference transitions from the ss/trk voltage to the internal voltage reference. when the comp pin voltage is clamped by the maximum comp clamp in an overload condition the soft-start pin is discharged to near the fb voltage. when the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. at the beginning of recovery a spike in the output voltage may occur as the comp voltage transitions to the value determined by the loop. 7.3.7 start-up into pre-biased output the tps54116-q1 features monotonic startup into pre-biased output. the low-side mosfet turns on for a very short time period every cycle before the output voltage reaches the pre-biased voltage. this ensures the boot- sw cap has enough charge to turn on the high-side mosfet when the output voltage reaches the pre-biased voltage. the low-side mosfet reverse current protection provides another layer of protection but it should not be reached due to the implemented prebias function. 7.3.8 power good the pgood pin is an open-drain output requiring an external pullup resistor to output a high signal. once the fb pin is between 94% and 106% of the internal voltage reference, the pgood pin is de-asserted and the pin floats. a pull up resistor between the values of 10 k ? and 100 k ? to a voltage source that is 6 v or less is recommended. the pgood is in a defined state once the avin input voltage is greater than 1.3 v but with reduced current sinking capability. the pgood pin is pulled low when the fb is lower than 91% or greater than 109% of the nominal internal reference voltage. the pgood is also pulled low if avin falls below its uvlo, ensw pin is pulled low or the tps54116-q1 enters thermal shutdown. u ss ss c nf 5.3 t ms ent enfalling enb stop enfalling ent p h r v r v v r i i u u enfalling start stop enrising ent enfalling p h enrising v v v v r v i 1 i v u ? ? 1 u ? ? 1
20 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.9 sequencing many of the common power supply sequencing methods can be implemented using the ss/trk, ensw and pgood pins. the sequential method can be implemented using an open-drain or collector output of a power on reset pin of another device. an example sequential method is shown in figure 42 . pgood is connected to the en pin on the next power supply, which will enable the second power supply once the first supply reaches regulation. figure 42. sequential startup example 7.3.10 constant switching frequency and timing resistor (rt/sync) the switching frequency of the tps54116-q1 is adjustable over a wide range from 100 khz to 2500 khz by placing a maximum of 620 k and minimum of 22 k , respectively, on the rt/sync pin. alternatively the rt/sync pin can be tied above the high threshold or below the low threshold to use an internal rt resistor to set the switching frequency to 420 khz. the rt/sync is typically 0.5 v and the current through the resistor sets the switching frequency. to determine the timing resistance for a given switching frequency, refer to the curve in figure 16 and figure 17 or use equation 5 . for a given rt resistor the nominal switching frequency can be calculated with equation 6 . to reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. the minimum controllable on time is typically 60 ns at 2-a load current and 100 ns at no load, and will limit the maximum operating input voltage or minimum output voltage. (5) (6) the rt/sync pin can also be used to synchronize the converter to an external system clock. when using the internal rt resistor, the tps54116-q1 cannot be synchronized to an external clock. the synchronization frequency range is 100 khz to 2500 khz. the rising edge of sw will be synchronized to the rising edge of rt/sync. to implement the synchronization feature in a system connect a square wave to the rt/sync pin with on-time at least 10 ns. the square wave amplitude at this pin must transition lower than 0.35 v and higher than 2.2 v. see figure 43 for synchronizing to a high impedance system clock. see figure 44 and figure 45 for synchronizing to a low impedance system clock. a tri-state buffer with its output directly connected to the rt/sync pin is the recommended method to accomodate a wide range of external clock frequencies and duty cycles. alternatively an ac blocking capacitor circuit can be used when synchronizing to frequencies greater than 800 khz and with clock signals with duty cycle near 50%. when using an ac coupling capacitor to interface with an external clock, rt/sync is not actively pulled low by the external clock. as a result the tps54116-q1 begins its transition back to rt mode while the external clock is low. when connecting the rt/sync pin to the external clock source, it is important to minimize routing connected to the rt/sync pin as much as possible to minimize noise sensitivity when operating in rt mode. : t 1.033 sw 72540 r k f khz ensw tps54116-q1 ss/trk c ss pgood en 2nd dc/dc ss pgood c ss : sw 0.968 t 50740 f khz r k
21 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 43. synchronizing to a high impedance system clock figure 44. interfacing to the rt/sync pin with buffer figure 45. interfacing to the rt/sync pin with rc tps54116-q1 rt/sync r rt oscillator 22 pf 1 k tps54116-q1 rt/sync r rt oscillator oe tps54116-q1 rt/sync r rt oscillator
22 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.11 buck overcurrent protection the tps54116-q1 implements current mode control which uses the comp pin voltage to turn off the high-side mosfet and turn on the low-side mosfet on a cycle-by-cycle basis. each cycle the switch current and the comp pin voltage are compared, when the peak switch current intersects the comp voltage the high-side switch is turned off. during overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the comp pin high, increasing the switch current. the error amplifier output is clamped internally. this clamp functions as a high-side switch current limit. a resistor placed from ilim to agnd sets the peak current limit of the buck converter in the tps54116-q1. a 100 k resistor sets it to the maximum value and a 200 k resistor sets it to the minimum value. any resistor within this range can be used. figure 12 shows the relationship between peak current limit and ilim resistor. to determine the resistor value for a target current limit use equation 7 . vertical spacer (7) the tps54116-q1 also implements low-side current protection by detecting the voltage over the low-side mosfet. when the converter sinks current through the low-side mosfet is more than 4.5 a, the control circuit will turn the low-side mosfet off immediately for the rest of the clock cycle. under this condition, both the high- side and low-side are off until the start of the next cycle. 7.3.12 overvoltage transient protection the tps54116-q1 incorporates an overvoltage transient protection (ovtp) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients. the ovtp feature minimizes the output overshoot by implementing a circuit to compare the fb pin voltage to ovtp threshold which is 109% of the internal voltage reference. if the fb pin voltage is greater than the ovtp threshold, the high-side mosfet is disabled preventing current from flowing to the output and minimizing output overshoot. the output voltage can overshoot the 109% threshold as the current in the inductor discharges to 0 a. when the fb voltage drops lower than the ovtp threshold the high-side mosfet is allowed to turn on the next clock cycle. 7.3.13 vtt sink and source regulator the tps54116-q1 integrates a high-performance, low-dropout (ldo) linear regulator (vtt) that has ultimate fast response to track ? vddqsns within 40 mv at all conditions, and its current capability is 1.5 a peak current for both sink and source directions. two 10- f (or greater) ceramic capacitor(s) need to be attached close to the vtt pin for stable operation. x5r grade or better is recommended. to achieve tight regulation with minimum effect of trace resistance, the remote sensing terminal, vttsns, should be connected to the positive terminal of the output capacitor(s) as a separate trace from the high current path from the vtt pin. the device has a dedicated pin, vldoin, for vtt power supply to minimize the ldo power dissipation on user application. the minimum vldoin voltage is 0.45 v above the ? vddqsns voltage. 7.3.14 vttref the vttref pin has a 10 ma sink and source current capability, and regulates to within 49% to 51% of vddqsns. a 0.22- f ceramic capacitor needs to be attached close to the vttref terminal for stable operation. x5r grade or better is recommended. 7.3.15 thermal shutdown the device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175 c. the thermal shutdown has a hysteresis of 16 c. when the junction temperature exceeds thermal trip threshold, thermal shutdown forces the device to stop switching and discharges both vtt and vttref. when the die temperature decreases below 159 c, the device reinitiates the power-up sequence by discharging the ss/trk pin. u 0.75 ilim limit r 420 i
23 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.4 device functional modes the enable pins and an avin uvlo are used to control turn on and turn off of the tps54116-q1. the device becomes active when v (avin) exceeds the 2.7 v typical uvlo and when either v (ensw) or v (enldo) exceeds 1.20 v typical. the ensw pin is used to control the turn on and turn off of the buck converter. the enldo pin is used to control the turn on and turn off of the vttref and vtt outputs of the termination regulator. the ensw and enldo pins both have an internal current source to enable their respective outputs when left floating. both ensw and enldo need to be pulled low to put the device into a low quiescent current state.
24 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps54116-q1 is a fully integrated power solution for ddr2, ddr3 and ddr3l memory supplying vddq, vttref and vtt as shown in figure 46 . it can also be used to power lpddr2, lpddr3 and ddr4 memory but an additional power supply is required for vdd1 or vpp as shown in figure 47 . the tps54116-q1 can supply 4 a for vddq and 1 a for vtt. the sourcing current for vtt comes from vddq and must be included as part of the total vddq load current. use the following design procedure to select component values for the tps54116-q1. this procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. alternatively the webench ? software can be used to generate a complete design. the webench ? software uses an interactive design procedure and accesses a comprehensive database of components when generating a design. this section presents a simplified discussion of the design process. figure 46. ddr2, ddr3 and ddr3l application block diagram figure 47. lpddr2, lpddr3 and ddr4 application block diagram tps54116-q1 5.0 v or 3.3 v vddq vttref vtt tps57112-q1 or other dc/dc vpp or vdd1 copyright ? 2016, texas instruments incorporated tps54116-q1 5.0 v or 3.3 v vddq vttref vtt copyright ? 2016, texas instruments incorporated
25 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2 typical application figure 48. 3.3-v or 5-v input, 2.1 mhz fsw, ddr3 schematic 8.2.1 design requirements table 1. design parameters design parameters example values input voltage 5 v nominal, 2.95 v to 5.25 v output voltage 1.5 v maximum output current (vddq) 4 a maximum output current (vtt) 1 a output voltage ripple (vddq) 0.5% of v out transient response 1 a to 3 a load step v out = 4 % start input voltage (rising vin) 2.9 v stop input voltage (falling vin) 2.6 v 8.2.2 detailed design procedure 8.2.2.1 switching frequency the first step is to decide on a switching frequency for the regulator. the buck converter is capable of running from 100 khz to 2.5 mhz. typically the highest switching frequency possible is desired because it will produce the smallest solution size. a high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. additionally in applications with emi requirements, such as automotive, choosing a switching frequency of 2.1 mhz is desired to keep the switching noise above the medium wave band or am band. they main trade off made with selecting a higher switching frequency is extra switching power loss, which hurt the converter ? s efficiency. sw 1 boot 2 avin 3 ensw 4 enldo 5 pgood 6 vddqsns 7 ldoin 8 vtt 9 vttgnd 10 vttsns 11 vttref 12 ilim 13 agnd 14 fb 15 comp 16 ss/trk 17 rt/sync 18 pgnd 19 pgnd 20 pvin 21 pvin 22 sw 23 sw 24 pad 25 u1 tps54116qrtwrq1 10f c3 0.1f c2 47f c1 1.00k r6 22pf c9 26.7k r7 100k r3 180pf c7 1800pf c6 20.5k r6 3300pf c5 10.0k r15 15.0k r14 180pf c17 47f c13 47f c12 0.1f c10 10f c8 10f c16 10f c15 0.22f c11 agnd nt1 net-tie pgnd 680nh l1 1f c4 45.3k r1 30.1k r2 100k r5 47f c14 vttref vin vtt vttref vddq osc in
26 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated the maximum switching frequency for a given application is limited by the minimum on-time of the converter and is estimated with equation 8 . for this application with the maximum minimum on-time of 125 ns at no load and 5.25 v maximum input voltage the maximum switching frequency is 2.28 mhz. a switching frequency of 2.1 mhz is selected to stay above the am band. equation 9 calculates r14 to be 26.8 k . a standard 1% 26.7 k value was chosen in the design. (8) (9) 8.2.2.2 output inductor selection to calculate the value of the output inductor, use equation 10 . k ind is a ratio that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. additionally the inductor current ripple is used as part of the pwm control system. choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the duty cycle. in general, the inductor ripple value is at the discretion of the designer; however, k ind is normally from 0.1 to 0.3 for the majority of applications giving a peak to peak ripple current range of 0.4 a to 1.2 a. it is recommended to always keep the peak to peak ripple current above 0.4 a because with a current mode control the inductor current ramp is used in the pwm control system. for this design example, k ind = 0.3 is used and the inductor value is calculated to be 0.43 h. the next standard value 0.68 h is selected. it is important that the rms current and saturation current ratings of the inductor not be exceeded. the rms and peak inductor current can be found from equation 12 and equation 13 . for this design, the rms inductor current is 4.0 a and the peak inductor current is 4.4 a. the chosen inductor is a we 744373240068. it has a saturation current rating of 10.0 a (20% inductance loss) and a rms current rating of 5.5 a (40 c. temperature rise). the series resistance is 16.0 m typical. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the steady-state peak inductor current. additionally if a hard short on the output occurs in a fault condition the peak inductor current can exceed the current limit and may reach up to 10 a. the peak current limit in this scenario is only limited by the minimum on- time of the tps54116-q1 and the parasitic dc voltage drops in the circuit. the peak current during a hard short will vary with the switching frequency and only exceeds the current limit when using the tps54116-q1 with higher switching frequencies like 2.1 mhz. to protect the inductor in a hard output short the inductor should be rated for this current. (10) vertical spacer (11) vertical spacer (12) vertical spacer (13) - | vinmax vout vout iripple = l1 vinmax sw : t 1.033 sw 72540 r k f khz - | vinmax vout vout l1 = io kind vinmax sw out sw in v 1 f max tonmin v max u iripple ilpeak = iout + 2 ? ? - ? | ? 2 2 1 vo (vinmax vo) ilrms = io + 12 vinmax l1 sw
27 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2.3 output capacitor there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the more stringent of these three criteria. the desired response to a large change in the load current is the first criteria and is often the most stringent. the output capacitor needs to supply the increased load current until the regulator responds to the load step. the regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. the regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. the output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. at higher switching frequencies the fastest response time is about 4 s. equation 14 shows the minimum output capacitance necessary, where i out is the change in output current, tresponse is the regulators response time and v out is the allowable change in the output voltage. the minimum of 2/fsw or 4 s should be used for the response time in the output capacitance calculation. it is important to realize the response to a transient load also depends on the loop compensation and slew rate of the transient load. this calculation assumes the loop compensation is designed for the output filter with the equations later on in this procedure. for this example, the transient load response is specified as a 4% change in vout for a load step of 2 a. therefore, i out is 2 a and v out = 0.04 1.5 = 60 mv. using these numbers with a 4 s response time gives a minimum capacitance of 133 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to be ignored. aluminum electrolytic and tantalum capacitors have higher esr that must be considered for load step response. equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where fsw is the switching frequency, vripple is the maximum allowable output voltage ripple, and iripple is the inductor ripple current. in this case, the maximum output voltage ripple is 7.5 mv. under this requirement, equation 15 yields 6.3 f. vertical spacer (14) vertical spacer where: ? i out is the change in output current ? f sw is the regulators switching frequency ? v out is the allowable change in the output voltage (15) vertical spacer equation 16 calculates the maximum combined esr the output capacitors can have to meet the output voltage ripple specification and this shows the esr should be less than 10 m ? . in this case ceramic capacitors will be used and the combined esr of the ceramic capacitors in parallel is much less than 10 m ? . capacitors also generally have limits to the amount of ripple current they can handle without failing or producing excess heat. an output capacitor that can support the inductor ripple current must be specified. some capacitor data sheets specify the rms (root mean square) value of the maximum ripple current. equation 17 can be used to calculate the rms ripple current the output capacitor needs to support. for this application, equation 17 yields 220 ma. ceramic capacitors used in this design will have a ripple current rating much higher than 220 ma. (16) vertical spacer (17) - | vout (vinm ax vout) icorm s = 12 vinm ax l1 sw voripple resr < iripple 1 1 co > voripple 8 sw iripple | response iout co t vout ' ! u '
28 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated the value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. x5r and x7r ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias taken into account. the capacitance value of a capacitor decreases as the dc bias across a capacitor increases. for this application example, three 47 f 10 v 1210 x7r ceramic capacitors each with 8 m ? of esr at the fsw are used. the estimated capacitance after derating shown on the capcaitor manufacturer's website with 1.5 v dc bias is 51.4 f each. with 3 parallel capacitors the total output capacitance is 154 f and the esr is 2.7 m . 8.2.2.4 input capacitor the tps54116-q1 requires a high quality ceramic, type x5r or x7r, input decoupling capacitor of at least 10 f of effective capacitance placed across the pvin and pgnd pins and in some applications a bulk capacitance. the effective capacitance includes any dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum rms input current of the tps54116-q1. the rms input current can be calculated using equation 18 . an input decoupling capacitor of 1 f must also be placed at the avin pin to ensure a stable input voltage to the internal control circuits. for this example design, a ceramic capacitor with at least a 10 v voltage rating is required to support the maximum input voltage. for this example, one 47 f 1210 x7r, one 10 f 0603 x7r and one 0.1 f 0603 x7r 10 v capacitors in parallel have been selected for the pvin to pgnd pins. additionally one 1 f 0603 x5r 10 v capacitor is selected for the avin pin. the 0.1 f at the pvin pin is used to better bypass the higher frequency content when the high-side mosfet switches on and off. based on the capacitor manufacturer's website, the total input capacitance derates to 34 f at the nominal input voltage of 5 v. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 19 . using the design example values, ioutmax = 4 a, cin = 34 f, f sw = 2.1 mhz, yields an input voltage ripple of 14 mv and a rms input ripple current of 1.9 a. (18) vertical spacer (19) 8.2.2.5 soft start capacitor the soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps54116-q1 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. limiting the output voltage slew rate solves both of these problems. the soft-start capacitor value can be calculated using equation 20 . for the example circuit, the soft-start time is not too critical since the output capacitor value of 3 x 47 f does not require much current to charge to 1.5 v. with the higher switching frequency used in this example a faster start-up time improves the start up behavior. near the beginning of the start up time when the output voltage is low the minimum on-time of the converter is too large to regulate the output causing additional ripple on the output. a faster start-up time will reduce the time the converter spends in this region. the example circuit is designed for a soft-start time of 0.6 ms which requires a 3300 pf capacitor. (20) u ss ss c nf 5.3 t ms ioutmax 0.25 vin = cin sw d | ( ) vinmin vout vout icirms = iout vinmin vinmin -
29 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2.6 undervoltage lock out set point the undervoltage lock out (uvlo) can be adjusted using an external voltage divider on the ensw and enldo pin of the tps54116. each pin can have its own resistor divider if different thresholds are needed for the vtt ldo and the buck converter. if only one threshold is needed only one resistor divider is needed and the pins can be connected in parallel. if connected in parallel the pull up current and hysteresis current should be increased to 3.4 a and 5.1 a respectively as shown in the electrical specifications. the uvlo has two thresholds, one for power-up when the input voltage is rising, and one for power-down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 2.9 v (enabled). after the regulator starts switching, it should continue to do so until the input voltage falls below 2.6 v (uvlo stop). the en pins are also connected in parallel so the higher pull up current and hysteresis current is used. equation 2 through equation 3 can be used to calculate the resistance values necessary. a 45.3 k ? between pvin and the en pins (r1) and a 30.1 k ? between the en pins and ground (r2) are used producing a start voltage of 2.85 v and stop voltage of 2.47 v. the 2.47 v stop voltage is below the 2.65 v avin uvlo so with this application example the tps54116-q1 will turn off due to the avin uvlo. 8.2.2.7 bootstrap capacitor a 0.1 f ceramic capacitor must be connected between the boot and sw pins for proper operation. it is recommended to use a ceramic capacitor with x5r or better grade dielectric. the capacitor should have 10 v or higher voltage rating. 8.2.2.8 power good pullup a 100 k resistor is used to pull up the power good signal to vin when fb conditions are met. 8.2.2.9 ilim resistor the recommended peak current limit is calculated with equation 21 using ilpeak from equation 13 . this calculation includes 10% margin for load transients and an additional 1.5 a for the tolerance of the peak current limit. in this application a 100 k resistor is placed from ilim to agnd to set the peak current limit to its maximum value. for applications requiring a different peak current limit equation 7 is used to calculate the ilim resistor. vertical spacer (21) 8.2.2.10 output voltage and feedback resistors selection for the example design, 10.0 k ? was selected for r7. using equation 22 , r5 is calculated as 15.0 k ? which is a standard 1% resistor. vertical spacer (22) 8.2.2.11 compensation there are several methods used to compensate dc - dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. this method assumes the cross-over frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. this is the case when using low esr output capacitors. use the webench software for more accurate loop compensation. these tools include a more comprehensive model of the control loop. out fbt fbb ref v r r 1 v u ? ? 1 u limit i ilpeak 1.1 1.5a
30 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated to get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using equation 23 and equation 24 . for cout, use a derated value of 154 f. use equations equation 25 and equation 26 , to estimate a starting point for the crossover frequency, fco, to design the compensation. for the example design, fpmod is 2.8 khz and fzmod is 388 khz. equation 25 is the geometric mean of the modulator pole and the esr zero and equation 26 is the mean of modulator pole and one half the switching frequency or 250 khz, whichever is larger. for the 2.1 mhz switching frequency application 250 khz is used so equation 25 yields 33 khz and equation 26 gives 52 khz. use the lower value of equation 25 or equation 26 for an initial crossover frequency. next, the compensation components are calculated. a resistor-in-series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (23) (24) (25) (26) to determine the compensation resistor, r6, use equation 27 . assume the power stage transconductance, gmps, is 16 a/v. the output voltage, vo, reference voltage, vref, and amplifier transconductance, gmea, are 1.5 v, 0.6 v and 260 a/v, respectively. r6 is calculated to be 19 k ? and the closest standard value 19.1 k . use equation 28 to set the compensation zero to the modulator pole frequency. equation 28 yields 3020 pf for compensating capacitor c6 and the closest standard value is 3300 pf. (27) (28) a compensation pole is implemented using an additional capacitor c7 in parallel with the series combination of r6 and c6. this capacitor is recommended to help filter any noise that may couple to the comp voltage signal. use the larger value of equation 29 and equation 30 to calculate the c7, to set the compensation pole. c7 is calculated to 21 pf or 8 pf and the closest standard value is 22 pf. (29) (30) type iii compensation is used by adding the feed forward capacitor (c17) in parallel with the upper feedback resistor. this increases the crossover and adds phase boost above what is normally possible from type ii compensation. it places an additional zero/pole pair. this zero and pole pair is not independent. once the zero location is chosen, the pole is fixed as well. the zero is placed at the intended crossover frequency by calculating the value of c17 with equation 31 . the calculated value is 216 pf and the closest standard value is 220 pf. (31) the initial compensation based on these calculations is r6 = 19.1 k , c6 = 3300 pf, c7 = 22 pf and c17 = 220 pf. these values yield a stable design but after testing the real circuit these values were changed to optimize performance. the final values used in the schematic are r6 = 20.5 k , c6 = 1800 pf, c7 = 180 pf and c17 = 180 pf. 8.2.2.12 ldoin capacitor depending on the trace impedance between the ldoin bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the ldoin input capacitor. use a 10- f (or greater) and x5r grade (or better) ceramic capacitor to supply this transient charge. hf comp sw 1 c r f s u u out esr hf comp c r c r u comp comp pmod 1 c 2 r f u s u u co out out comp ps ref ea 2 f c v r gm v gm u s u u u ? ? u ? 1 ? 1 2 sw p f f f = co mod p z f f f = co mod mod 1 z mod = 2 resr cout | p ioutmax p mod = 2 vout cout | p u s u u ff fbt co 1 c 3 r f
31 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2.13 vttref capacitor add a ceramic capacitor, with a value 0.22 f and x5r grade (or better), placed close to the vttref terminal for stable operation. 8.2.2.14 vtt capacitor for stable operation, two 10- f (or greater) and x5r (or better) grade ceramic capacitor(s) need to be attached close to the vtt terminal. this capacitor is recommended to minimize any additional equivalent series resistance (esr) and/or equivalent series inductance (esl) of ground trace between the pgnd terminal and the vtt capacitor(s). 8.2.3 application curves figure 49. v dd output efficiency figure 50. v dd output load regulation, v in = 5 v figure 51. v dd output line regulation, i out = 2 a figure 52. v dd output loop response output current (a) efficiency (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 50 60 70 80 90 100 d037 v in = 5v output current (a) load regulation (%) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 d039 input voltage (v) line regulation (%) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 d041 frequency (hz) gain (db) phase (degree) 100 200 500 1000 10000 100000 500000 -60 -180 -50 -150 -40 -120 -30 -90 -20 -60 -10 -30 0 0 10 30 20 60 30 90 40 120 50 150 60 180 d043 gain (db) phase (deg)
32 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated figure 53. v dd start-up relative to enable figure 54. v tt and v dd start-up relative to enable figure 55. v dd start-up relative to v in figure 56. v dd shutdown relative to enable figure 57. v tt and v dd shutdown relative to enable figure 58. v dd shutdown relative to v in v = 1 v / div tt time = 1 msec / div en = 2 v / div v = 1 v / div dd pgood = 5 v / div v = 5 v / div in time = 1 msec / div v = 1 v / div dd ss = 1 v / div pgood = 5 v / div v = 5 v / div in time = 1 msec / div v = 1 v / div dd ss = 1 v / div pgood = 5 v / div time = 1 msec / div en = 2 v / div v = 1 v / div dd ss = 1 v / div pgood = 5 v / div time = 1 msec / div en = 2 v / div v = 1 v / div dd ss = 1 v / div pgood = 5 v / div v = 1 v / div tt time = 1 msec / div en = 2 v / div v = 1 v / div dd pgood = 5 v / div
33 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated figure 59. v dd output ripple figure 60. v tt output ripple figure 61. input ripple figure 62. v dd output transient response figure 63. v tt output transient response v = 50 mv / div (ac coupled) dd time = 200 sec / div i = 1a / div out load step 1 a to 3 a, slew rate 500 ma / sec v = 10 mv / div (ac coupled) dd time = 500 nsec / div sw = 2 v / div v = 20 mv / div (ac coupled) tt time = 500 nsec / div sw = 2 v / div v = 20 mv / div (ac coupled) tt time = 100 sec / div clk = 2 v / div v = 100 mv / div (ac coupled) in time = 500 nsec / div sw = 2 v / div
34 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 9 power supply recommendations the tps54116-q1 is designed to be powered by a well regulated dc voltage between 2.95 and 6 v. the tps54116-q1 is a buck converter so the input supply voltage must be greater than the desired output voltage to regulate the output voltage to the desired value. if the input supply voltage is not high enough the output voltage will begin to drop. input supply current must be appropriate for the desired output current. 10 layout 10.1 layout guidelines layout is a critical portion of good power supply design. there are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. guidelines are as follows. see figure 64 for a pcb layout example. ? the input bypass capacitor for pvin to pgnd should be placed as close as possible to the tps54116-q1 with short and wide connections to minimize parasitic inductance. ? the input bypass capacitor for avin should be placed as close as possible to the tps54116-q1 with a short return to the agnd pin. this capacitor and pin should also be tied to the input voltage before the pvin bypass capacitors to limit the switching noise from pvin. ? the output capacitor for vtt to vttgnd should be placed as close as possible to the tps54116-q1 with short and wide connections to minimize parasitic inductance and resistance. too much parasitic inductance and resistance can affect the stability of the high performance vtt ldo. ? the vttsns pin should be connected tothe vtt output capacitors as a seperate trace from the high current vtt power trace. if sensing the voltage at the pont of the load is required, it is recommended to also attach the output capacitors at that point while still minimizing parasitic inductance and resistance. ? the input bypass capacitor for ldoin to vttgnd should be placed as close as possible to the tps54116- q1 with short and wide connections to minimize parasitic inductance. this capacitor is used to supply the transient current to the vtt output. ? the vddqsns pin should be routed as a separate trace from the high current vddq trace and connect near the point of regulation for vddq. ? the top of the fb resistor divider should be routed as a separate trace from the high current vddq trace and connect near the the point of regulation for vddq. ? the analog control circuits should have a return path to the quiet agnd and not overlap with the noisey pgnd. sensitive pins containing analog control circuits are rt/sync, ss/trk, comp, fb, ilim, and vttref. it is important to minimize the length of the traces connected to the rt/sync, comp, fb and ilim pins. ? the pgnd pins, agnd and vttgnd pin should be tied directly to the power pad under the ic to provide a low impedance connection between the pins. ? the boot capacitor should connect directly between the boot and sw pins. ? the sw pin should be routed to the output inductor with a short and wide trace to minimize capacitive coupling. ? the thermal pad should be connected to any internal pcb ground planes using multiple vias directly under the ic. for operation at full rated load, the top side ground area and bottom side ground area along with any additional internal ground planes must provide adequate heat dissipating area. for best thermal performance minimize cuts in the bottom side ground copper. ? additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors for the buck converter and vtt ldo. the additional external components can be placed approximately as shown. it may be possible to obtain acceptable performance with alternate pcb layouts, however this layout has been shown to produce good results and is meant as a guideline.
35 tps54116-q1 www.ti.com slvsco3a ? august 2016 ? revised august 2016 product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 10.2 layout example figure 64. pcb layout example sw boot ensw pgood avin enldo sw pvin pgnd pvin pgnd sw rt/ sync agnd ss/ trk ilim fb comp vttref ldoin vtt vttgnd vddqsns vttsns 6 5 4 3 2 1 78 9 10 11 12 thermal pad 24 23 22 21 20 19 13 14 15 16 17 18 cin l cout c ldoin cin c ref c bt r pg r enb r enb r ent c vtt c vtt cin cout cout cout r fbt c ff r ilim r fbb c hf r cp c cp c ss r t r ent gnd vin gnd vout sw vtt gnd vref
36 tps54116-q1 slvsco3a ? august 2016 ? revised august 2016 www.ti.com product folder links: tps54116-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 23-aug-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps54116qrtwrq1 active wqfn rtw 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 54116q a2 TPS54116QRTWTQ1 active wqfn rtw 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 54116q a2 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 23-aug-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps54116qrtwrq1 wqfn rtw 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 TPS54116QRTWTQ1 wqfn rtw 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 25-aug-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps54116qrtwrq1 wqfn rtw 24 3000 367.0 367.0 35.0 TPS54116QRTWTQ1 wqfn rtw 24 250 210.0 185.0 35.0 package materials information www.ti.com 25-aug-2016 pack materials-page 2
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